This invention relates to a weighted capacitor analogue-digital converter and, more particularly, to a weighted capacitor analogue-digital converter having a resistance voltage divider.
One type of analogue-digital converter was developed in California University in United States and one example of an 8 bit weighted capacitor analogue-digital inverter is illustrated in FIG. 1 of the accompanying drawing.
In FIG. 1 each one of the capacitors 103 and 104 has a unit capacity, while capacitors 105 through 111 respectively have weighted capacities of twice, 4 times, 8 times, 16 times, 32 times, 64 times, and 128 times the unity capacity. These capacitors constitute a capacitor array and are formed on a semiconductor substrate through parallelly connected unit MOS capacitances.
Each of the switches 112 through 119 has one movable contact and two stationary contacts. Respective movable contacts of the switches are respectively connected to a line L.sub.1 via capacitors 104 through 111 the left-hand stationary contacts are connected to a line L.sub.2 and the right-hand stationary contacts are connected to a reference voltage input terminal 122.
A switch 101 is provided with a movable contact connected to line L.sub.1, an idle stationary contact and a grounded stationary contact. Another switch 120 is provided with a movable contact connected to line L.sub.2, a stationary contact connected to an analogue signal input terminal 121 and a grounded second stationary contact. A capacitor 103 is connected between lines L.sub.1 and L.sub.2. Since the non-inverting input of a comparator 102 is connected to ground, it is normally necessary to use two power supplies (i.e.--one positive supply and one negative supply) to power the comparator 102.
An inverting input terminal of the comparator 102 in the form of a differential amplifier is connected to line L.sub.1, while a noninverting input terminal is grounded and its output terminal is connected to a control signal input terminal of a sequentially comparing register 127 which outputs a switch control code signal 128 consisting of 8 bits, for example, for controlling the switches 112 through 119. The switch control code signals 128 are also applied to a latch circuit 129 to be temporarily stored therein.
A timing signal generator 125 has a clock signal input terminal 123 supplied with a clock signal of a constant period and a synchronizing signal input terminal 124 supplied with a synchronizing signal which sets the analogue-digital converter to an initial state, and produces timing signals 126 which control the switches 101 and 120 and which controls the sequentially comparing register 127 according to a predetermined sequence.
The digital-analogue converter shown in FIG. 1 operates as follows. Upon application of a synchronizing signal to the synchronizing signal input terminal 124, the timing signal 126 sets the analogue-digital converter to its initial state for connecting the movable contact of the switch 120 to the analogue signal input terminal 121 and for grounding the movable contact of the switch 101. At the same time, the eight bit switch control code signal 128 becomes "00000000" so as to transfer the movable contacts of respective switches 112 through 119 to the line L.sub.2. As a consequence, capacitors 103 through 111 are parallelly connected between the analogue signal input terminal 121 and the ground so that these capacitors are charged by the input signal voltage V.sub.in applied to the analogue signal input terminal 121.
When the movable contact of the switch 120 is transferred to the lower stationary contact to ground the line L.sub.2 in response to the timing signal of the first operating cycle and when the movable contact of the switch 101 is transferred to the idle stationary contact to disconnect the line L.sub.1 from the ground, the voltage V.sub.x applied to the inverting contact of the comparator 102 would become -V.sub.in.
From this state, the comparator 102 starts its sequential comparison operation. To obtain the most significant bit of the digital output signal, the most significant bit of the switch control code signal 128 is made to be "1" by the timing signal of the second operating cycle, while the movable contact of the switch 119 is transferred to the right-hand stationary contact connected to the reference voltage input terminal 122.
Consequently, a capacitor voltage division circuit including two serially connected capacitors each having a capacitance of 128C.sub.x is formed between the reference voltage input terminal 122 and the ground to raise the voltage of the line L.sub.1 by V.sub.Ref /2 so that the voltage V.sub.x applied to the noninverting input terminal of the comparator 102 would be changed to (-V.sub.in +V.sub.Ref /2).
Then, the comparator 102 compares the ground potential with the voltage V.sub.x applied to the inverting input terminal so that when the output of the comparator 102 is "1", the most significant bit of the switch control code signal 128 becomes "1" with the result that the movable contact of the switch 119 is continuously connected to the reference voltage input terminal 122. On the other hand, when the output of the comparator 102 is "0", the most significant bit of the switch control code signal 128 becomes "0" with the result that the movable contact of the swtich 119 will be connected to line L.sub.2 and maintained at the ground potential.
The timing signal 126 of the third operating cycle brings to "1" a bit next to the most significant bit of the switch control code signal 128 to transfer the movable contact of the switch 118 to the side of the reference voltage input terminal 122 whereby a new capacitance voltage dividing circuit is formed between the same and the ground so that a fraction of the reference voltage is superposed upon the voltage of the line L.sub.1 obtained in the previous cycle.
These superposed voltages are applied to the noninverting input terminal of the comparator 102, and if the output thereof were "1", the bit next to the most significant bit (MSB) of the switch control code signal 128 would become "1" so that the movable contact of the switch 118 is still connected to the reference voltage input terminal 122, whereas when the output of the comparator 102 is "0", the bit next to the most significant bit of the switch control code signal 128 becomes "0" so that the movable contact of the switch 118 is connected to line L.sub.2 to be maintained at the ground potential.
In the same manner, the logic values to the least significant bit (LSB) of the switch control code signal 128 are determined by the timing signals 126 of a series of the operating cycles. After all bit values of the switch control code signal 128 obtained by the sequence control have been temporarily stored in the latch circuit 129, these bit values are outputted as digital output signals 130 corresponding to the analogue input signal voltage V.sub.in.
The analogue-digital converter shown in FIG. 1, however, requires 256 unit capacitors of the capacitor array in the case of an 8 bit analogue-digital converter, for example, so that when the converter is fabricated as a monolithic integrated circuit the area occupied by the capacitor array on a semiconductor substrate becomes extremely large, thus increasing the chip size of the integrated circuit. This makes it difficult to construct a microcomputer as a single chip. In addition, the two power supply requirement for the comparators further complicates the construction of the system on a single chip.